integrated device technology, inc. military and commercial temperature ranges may 1992 1992 integrated device technology, inc. 7.18 dsc-4626/2 the idt logo is a registered trademark of integrated device technology, inc. fast is a registered trademark of national semiconductor co. idt54/74fct646 idt54/74fct646a idt54/74fct646c features: idt54/74fct646 equivalent to fast ? speed; idt54/74fct646a 30% faster than fast idt54/74fct646c 40% faster than fast independent registers for a and b buses multiplexed real-time and stored data ? ol = 64ma (commercial) and 48ma (military) cmos power levels (1mw typical static) ttl input and output level compatible cmos output level compatible available in 24-pin (300 mil) cerdip, plastic dip, soic, cerpack and 28-pin lcc product available in radiation tolerant and radiation enhanced versions military product compliant to mil-std-883, class b description: the idt54/74fct646/a/c consists of a bus transceiver with 3-state d-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. the idt54/74fct646/a/c utilizes the enable control ( g ) and direction (dir) pins to control the transceiver functions. sab and sba control pins are provided to select either real time or stored data transfer. the circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real- time data. a low input level selects real-time data and a high selects stored data. data on the a or b data bus or both can be stored in the internal d flip flops by low-to-high transitions at the appropriate clock pins (cpab or cpba) regardless of the select or enable control pins. fast cmos octal transceiver/register functional block diagram 2536 drw 01 1d c 1 a reg a 1 1d c 1 b reg b 1 to 7 other channels 1 of 8 channels sab cpba cpab sba dir g 1
7.18 2 idt54/74fct646/a/c fast cmos octal transceiver/register military and commercial temperature ranges pin configurations lcc top view dip/soic/cerpack top view function table (2) inputs data i/o (1) operation or function g g dir cpab cpba sab sba a 1 ? 8 b 1 ? 8 idt54/74fct646 h x h or l h or l x x input input isolation hx -- x x store a and b data l l x x x l output input real-time b data to a bus l l x h or l x h stored b data to a bus l h x x l x input output real-time a data to b bus l h h or l x h x stored a data to b bus notes: 2536 tbl 02 1. the data output functions may be enabled or disabled by various signals at the g or dir inputs. data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. 2. h = high, l = low, x = dont care, - = low-to-high transition. pin description pin names description a 1 Ca 8 data register a inputs data register b outputs b 1 Cb 8 data register b inputs data register a outputs cpab, cpba clock pulse inputs sab, sba output data source select inputs dir, g output enable inputs 2536 tbl 01 logic symbol 5 6 7 8 9 10 11 12 gnd a 1 a 2 a 3 1 2 3 4 24 23 22 21 20 19 18 17 vcc 16 15 14 13 cpab p24-1, d24-1, s024-2 & e24-1 b 1 a 4 a 5 a 6 sab dir a 7 a 8 cpba sba g b 2 b 3 b 4 b 5 b 6 b 7 b 8 2536 drw 06 cpab sab dir cpba sba g a 1 b 1 a 2 b 2 a 3 b 3 a 4 b 4 a 5 b 5 a 6 b 6 a 7 b 7 a 8 b 8 5 6 7 8 9 10 11 l28-1 25 24 23 22 21 20 19 index 2536 drw 02 b 1 g b 2 b 3 b 4 b 5 nc a 1 a 2 a 3 a 4 a 5 a 6 nc vcc cpab sab dir cpba sba nc gnd a 7 a 8 b 8 b 7 b 6 nc 12 13 14 15 16 17 18 432 1 28 27 26
idt54/74fct646/a/c fast cmos octal transceiver/register military and commercial temperature ranges 7.18 3 bus a bus b dir l g l cpab x cpba x sab x sba l 2536 drw 03 bus a bus b dir h g l cpab x cpba x sab l sba x bus a bus b dir h l x g l l h cpab x cpba x sab x x x sba x x x 2536 drw 04 bus a bus b dir l h g l l cpab x h or l cpba h or l x sab x h sba h x (1) storage from a and/or b real?ime transfer bus b to bus a real?ime transfer bus a to bus b transfer stored data to a and/or b note: 1. cannot transfer data to a bus and b bus simultaneously.
7.18 4 idt54/74fct646/a/c fast cmos octal transceiver/register military and commercial temperature ranges absolute maximum ratings (1) symbol rating commercial military unit v term (2) terminal voltage C0.5 to +7.0 C0.5 to +7.0 v with respect to gnd v term (3) terminal voltage C0.5 to v cc C0.5 to v cc v with respect to gnd t a operating 0 to +70 C55 to +125 c temperature t bias temperature C55 to +125 C65 to +135 c under bias t stg storage C55 to +125 C65 to +150 c temperature p t power dissipation 0.5 0.5 w i out dc output current 120 120 ma notes: 2536 tbl 03 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed v cc by +0.5v unless otherwise noted. 2. inputs and v cc terminals only. 3. outputs and i/o terminals only. capacitance (t a = +25 c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c i/o i/o capacitance v out = 0v 8 12 pf note: 2536 tbl 04 1. this parameter is measured at characterization but not tested. dc electrical characteristics over operating range following conditions apply unless otherwise specified: v lc = 0.2v; v hc = v cc C 0.2v commercial: t a = 0 c to +70 c, v cc = 5.0v 5%; military: t a = C55 c to +125 c, v cc = 5.0v 10% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2.0 v v il input low level guaranteed logic low level 0.8 v i ih input high current v cc = max. v i = v cc 5 m a (except i/o pins) v i = 2.7v 5 (4) i il input low current v i = 0.5v C5 (4) (except i/o pins) v i = gnd C5 i ih input high current v cc = max. v i = v cc 15 m a (i/o pins only) v i = 2.7v 15 (4) i il input low current v i = 0.5v C15 (4) (i/o pins only) v i = gnd C15 v ik clamp diode voltage v cc = min., i n = C18ma C0.7 C1.2 v i os short circuit current v cc = max. (3) , v o = gnd C60 C120 ma v oh output high voltage v cc = 3v, v in = v lc or v hc , i oh = C32 m av hc v cc v v cc = min. i oh = C300 m av hc v cc v in = v ih or v il i oh = C12ma mil. 2.4 4.0 i oh = C15ma coml. 2.4 4.0 v ol output low voltage v cc = 3v, v in = v lc or v hc , i ol = 300 m a gnd v lc v v cc = min. i ol = 300 m a gnd v lc (4) v in = v ih or v il i ol = 48ma mil. 0.3 0.55 i ol = 64ma coml. 0.3 0.55 notes: 2536 tbl 05 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second. 4. this parameter is guaranteed but not tested.
idt54/74fct646/a/c fast cmos octal transceiver/register military and commercial temperature ranges 7.18 5 power supply characteristics v lc = 0.2v; v hc = v cc C 0.2v symbol parameter test conditions (1) min. typ. (2) max. unit i cc quiescent power supply current v cc = max. 0.2 1.5 ma v in 3 v hc ; v in v lc d i cc quiescent power supply current v cc = max. 0.5 2.0 ma ttl inputs high v in = 3.4v (3) i ccd dynamic power supply current (4) v cc = max. v in 3 v hc 0.15 0.25 ma/mhz outputs open v in v lc g = dir = gnd one input toggling 50% duty cycle i c total power supply current (6) v cc = max. v in 3 v hc 1.7 4.0 ma outputs open v in v lc f cp = 10mhz (fct) 50% duty cycle g = dir = gnd v in = 3.4v 2.2 6.0 one bit toggling v in = gnd at fi = 5mhz 50% duty cycle v cc = max. v in 3 v hc 7.0 12.8 (5) outputs open v in v lc f cp = 10mhz (fct) 50% duty cycle g = dir = gnd v in = 3.4v 9.2 21.8 (5) eight bits toggling v in = gnd at f i = 5mhz 50% duty cycle notes: 2536 tbl 06 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an output transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz.
7.18 6 idt54/74fct646/a/c fast cmos octal transceiver/register military and commercial temperature ranges switching characteristics over operating range 54/74fct646 54/74fct646a 54/74fct646c com?. mil. com?. mil. com?. mil. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. min. (2) max. min . (2) max. unit t plh propagation c l = 50 pf 2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 1.5 5.4 1.5 6.0 ns t phl delay r l = 500 w bus to bus t pzh output enable 2.0 14.0 2.0 15.0 2.0 9.8 2.0 10.5 1.5 7.8 1.5 8.9 ns t pzl time g , dir to bus t phz output disable 2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 1.5 6.3 1.5 7.7 ns t plz time g , dir to bus t plh propagation 2.0 9.0 2.0 10.0 2.0 6.3 2.0 7.0 1.5 5.7 1.5 6.3 ns t phl delay clock to bus t plh propagation 2.0 11.0 2.0 12.0 2.0 7.7 2.0 8.4 1.5 6.2 1.5 7.0 ns t phl delay sba or sab to bus t su set-up time 4.0 4.5 2.0 2.0 2.0 2.0 ns high or low bus to clock t h hold time 2.0 2.0 1.5 1.5 1.5 1.5 ns high or low bus to clock t w clock pulse 6.0 6.0 5.0 5.0 5.0 5.0 ns width high or low notes: 2536 tbl 07 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays.
idt54/74fct646/a/c fast cmos octal transceiver/register military and commercial temperature ranges 7.18 7 test circuits and waveforms test circuits for all outputs enable and disable times propagation delay set-up, hold and release times pulse width pulse generator data input timing input asynchronous control preset clear etc. synchronous control preset clear clock enable etc. 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v t su t h t rem h t su r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v same phase input transition 3v 1.5v 0v 1.5v v oh v ol t plh t phl output opposite phase input transition control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol v oh 3v 1.5v 0v t plh t phl 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable high-low-high pulse low-high-low pulse t w 1.5v 1.5v t notes 2536 drw 07 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0 mhz; z o 50 w ; t f 2.5ns; t r 2.5ns. switch position test switch open drain disable low closed enable low all other tests open definitions: 2536 tbl 08 c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
7.18 8 idt54/74fct646/a/c fast cmos octal transceiver/register military and commercial temperature ranges ordering information xx package x process/ temperature range blank b commercial mil-std-883, class b p d so l e plastic dip cerdip small outline ic leadless chip carrier cerpack 646 646a 646c non-inverting octal transceiver/register fast non-inverting octal transceiver/register super fast non-inverting octal transceiver/register xxxx device type 2536 drw 05 54 75 C55 c to +125 c 0 c to +70 c fct temperature range xx idt
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